Nonvolatile semiconductor memory devices represented by NAND flash memories are manufactured by using semiconductor wafer processes. An increase in capacity and a reduction in power consumption and cost of the nonvolatile semiconductor memory devices have been realized in parallel with progress in two-dimensional miniaturization techniques for the wafer processes. On the other hand, memory devices that include a three-dimensional memory array having a plurality of memory layers laid on each other are being developed as next-generation nonvolatile memory devices. In order to increase the capacity of a three-dimensional memory cell array, it is necessary to miniaturize a plurality of word lines controlling memory cells and increase the number of stacks in the memory cell array. However, the miniaturization of the word lines and the increased number of stacks could cause the stacked structure of the memory cell array to collapse in some cases.